Invited Talks
Conference Speakers
Stephan Ulamec, DLR, Germany
Exploring New Worlds: The Rosetta/Philae Mission and its Challenges to Computer Architecture
Philae a comet Lander which is part of the ESA Rosetta mission successfully landed on comet
67P/Churyumov-Gerasimenko on November 12th, 2014. The landing followed a careful landing site
selection process based on data obtained with the Rosetta orbiter instruments.
After several (unplanned) bounces Philae performed a First Scientific Sequence (FSS), based on the energy
stored in it’s on board batteries. The touch-down dynamics, bouncing trajectory and attitude could be
reconstructed a-posteriori.
All ten instruments of the Philae payload have been operated at least once. Due to the fact that the final
landing site was poorly illuminated, Philae went into hibernation on November 15th, but signals
from the Lander were received again in June and July 2015. However, attempts to re-establish reliable
and stable communications links, unfortunately, failed. September 2nd, 2015, Philae could be clearly
identified on the comet surface with the Rosetta Orbiter (OSIRIS) Camera. Shortly after,
September 30th, the Rosetta mission was ended, by a planned impact of the main spacecraft on the
nucleus.
The development of the Rosetta Lander goes back to the mid 1990ies, consequently electronics in general and
its Command and Data Management System (CDMS) in particular, are based on (conservative) technology, available
20 years before the actual scientific operations! In order to combine radiation tolerance, high reliability
(flight heritage) and low power consumption, two redundant RTX2010 16-bit processors, manufactured by Harris
Semiconductor, have been used. Telemetry could be stored in a redundant mass memory with two times 16 Mbit
capacity.
Rosetta is an ESA mission with contributions from its member states and NASA. Rosetta's Philae Lander is
provided by a consortium led by DLR, MPS, CNES and ASI with additional contributions from Hungary, UK, Finland,
Ireland and Austria.
Chris Goodyer, ARM
ARM HPC : Supercomputing on a Lower Power Budget
ARM is the world's leading architecture, used in everything from almost
every modern mobile phone to tiny processors embedded in the rapidly
growing world of IoT devices. We work with over 1200 partners to deliver
an entire hardware and software ecosystem to help seamlessly deploy our
technology wherever computing happens. In 2012 ARM launched its 64-bit
instruction set and, since then, the worlds of enterprise server, data
centres and high performance computing have all opened up. ARM-powered
servers are already available from silicon partners including Cavium, AMD,
Applied Micro and nVidia.
In this presentation we will explore the growing ARM HPC ecosystem,
highlighting the movement from early adopters into real HPC deployments.
Work including the availability of the open source OpenHPC stack will be
explained, along with the development of the commercial tools that are
needed for real HPC systems.
The headline forthcoming system is Japan’s Post-K supercomputer, intended
to be an exascale system available in around 2021. This machine will be
built on the new ARM Scalable Vector Extension (SVE), which allows chip
designers to build systems with vector lengths of up to 2048 bits. The
presentation will also include an explanation of how SVE allows vector
instructions to be written without knowing the vector length in advance of
execution.
Short Bio: Based at ARM's Manchester Design Centre, Chris leads the ARM Performance
Libraries development team. They are responsible for optimizing the ARM
vendor maths library, which provides BLAS, LAPACK and FFT functionality.
He is also heavily involved in developing the ARM HPC software ecosystem.
He holds a PhD from the University of Leeds on efficient adaptive methods
for the numerical solution of PDEs and he subsequently worked at the
university for twelve years on research on a variety of HPC and numerical
modelling projects. Before joining ARM he was part of the HPC team at NAG
working on supporting national HPC services such as HECToR, the UK's
supercomputer, and the EU exascale project EXA2CT.
Barbara Chapman, SUNY Stonybrook
Parallel Heterogeneous Node Programming: A Work in Progress
Individual laptops, desktops and the compute nodes of HPC systems have undergone a remarkable transformation over the past 15 years. Starting as (in retrospect) simple uniprocessor architectures with a few levels of cache, today they are powerful parallel heterogeneous systems with an increasingly complex memory subsystem. As computer hardware designers learn how to provide even more performance with acceptable power consumption, this evolution continues.
Early mainstream programming models and application programming interfaces to exploit intra-node parallelism made direct use of the multicore system’s major characteristic: the ability to support multiple independent execution streams, or threads, that share memory. Yet today’s platforms are much more complex, with a large core count, non-uniform access and potentially disjoint memories.
In this talk, I will discuss the development of approaches to parallel programming on the node, challenges posed by significant changes in both applications and architectures, and potential future paths.
Short Bio: Dr. Chapman is a Professor of Applied Mathematics & Statistics and of Computer Science at Stony Brook University. She also directs Mathematics and Computer Science at Brookhaven National Laboratory. She has performed research into parallel programming models and their implementation for over 15 years, with a focus on OpenMP, OpenACC and OpenSHMEM.
Workshop Speakers
Jean Botev, University of Luxembourg
Collective Dynamics and Self-Optimisation in Large-Scale Networked Computer Systems
(Workshop: SAOS)
Today’s networked computer systems have reached a complexity
and scale that pushes existing modes of operation to their limits and
beyond. Developing adequate self-adaptation and self-optimisation
mechanisms therefore is vital for the reliable and robust provision of
services and maintenance of the underlying system infrastructures.
Cross-layer and system-of-systems aspects present further challenges in
their design. Understanding and taking advantage of the collective
dynamics in such systems is crucial for implementing decentralized,
self-organized solutions.
In this talk I will discuss fundamental issues and approaches for
environments characterized by a high degree of uncertainty and
unpredictability.
Short Bio: Dr. Botev is a senior researcher at the Computer Science and
Communications (CSC) research unit of the Faculty of Science,
Communication and Technology (FSTC) at the University of Luxembourg.
His background is in Computer Science and Media Studies. Before joining
the University in 2009, he was at the University of Trier (Germany) and
City University, London (UK). His research interests include complex
networks, self-organization, and collaborative socio-technical systems.
Dinner Speech
Arndt Bode, Chairman of the Board of Directors, Leibniz Supercomputing Centre and TU Munich
From Mailüfterl to VSC-X and SuperMUC
